A flash Analogue to Digital Converter (ADC), also known as a direct conversion ADC, uses a linear voltage ladder with a comparator at each ‘rung’ of the ladder, in order to compare the input voltage to successive reference voltages that are provided by successive rungs of the voltage ladder. Typically the voltage ladder comprises a plurality of resistors that are connected in series; although it has been shown that capacitive voltage division is also possible.
A benefit of flash ADCs is that they are extremely fast compared to many other types of ADCs that typically use a multi-stage approach to fine tune to the ‘correct’ digital value. Furthermore, flash ADCs tend to be relatively simple to implement, and apart from the analogue comparators used in the ADC, they only require logic for final conversion from a digital signal to a binary value.
FIG. 1 illustrates an example of a conventional 2-bit flash ADC circuit 100. The converter circuit 100 comprises a voltage ladder 110 for providing threshold voltages. In particular for the illustrated example, the voltage ladder 110 is in a form of a resistor string comprising two resistors 112, 114 connected in series between a reference voltage 116 and ground 118, such that the reference voltage 116 is divided across the resistors 112, 114 to provide three threshold voltage values 120, 130, 140.
The converter circuitry 100 of FIG. 1 further comprises three comparators 122, 132, 142. Positive inputs of comparators 122, 132, 142 are connected to an input voltage 150, whilst negative inputs of comparators are connected to the threshold voltage values 120, 130, 140 respectively. In this manner, the first comparator 122 performs a comparison of the input voltage 150 to the first threshold voltage 120 and outputs an indication of whether the input voltage 150 is higher or lower than the first threshold voltage 120; the second comparator 132 performs a comparison of the input voltage 150 to the second threshold voltage 130 and outputs an indication of whether the input voltage 150 is higher or lower than the second threshold voltage 130; and the third comparator 142 performs a comparison of the input voltage 150 to the third threshold voltage 140 and outputs an indication of whether the input voltage 150 is higher or lower than the third threshold voltage 140. The outputs of the comparators 122, 132, 142 are operably coupled to binary conversion logic 160, which outputs a 2-bit value based on the indications received from the comparators 122, 132, 142.
In an integrated system, for example in a case where a flash ADC forms a part of an integrated circuit device, the supply and ground lines typically experience significant amounts of noise, which can greatly affect the performance accuracy of a circuit. In order to reduce the effect of such noise, it is desirable to use differential signals, which are more tolerant of noise present on the supply and ground lines.
FIG. 2 illustrates an example of a known 2-bit flash ADC circuit 200 adapted to support differential signals. In the same manner as for the converter circuit 100 of FIG. 1, the converter circuit 200 of FIG. 2 comprises a voltage ladder 210 for providing threshold voltages. In particular for the illustrated example, the voltage ladder 210 is in a form of a resistor string comprising two resistors 212, 214 connected in series between a reference voltage 216 and ground 218, such that the reference voltage 216 is divided across the resistors 212, 214 to provide three threshold voltage values 220, 230, 240.
The converter circuitry 200 of FIG. 2 further comprises three comparators 222, 232, 242 comprising differential input ports. A first differential input of each comparator 222, 232, 242 is connected to a differential input signal 250, whilst a second differential input of each comparator 222, 232, 242 is connected to two of the threshold voltage values 220, 230, 240 as follows to provide differential threshold signals. The second differential input of the first comparator 222 is connected to the first threshold voltage 220 (as a positive differential input signal) and the third threshold voltage 240 (as a negative differential input signal). In this manner, the first comparator 222 performs a comparison of the differential input signal 250 to a differential threshold signal provided by the first and third threshold voltages 220, 240, and outputs an indication of whether the differential input signal 250 is higher or lower than the differential threshold signal provided by the first and third threshold voltages 220, 240. The second threshold voltage 230 provides both the positive and negative differential input signals for the second differential input of the second comparator 232. In this manner, the second comparator 232 performs a comparison of the differential input signal 250 to a differential threshold signal provided by the second threshold voltage 230 (which in this case will be a common voltage signal), and outputs an indication of whether the differential input signal 250 is higher or lower than the differential threshold signal provided by the second threshold voltage (i.e. effectively indicating whether the differential input signal 250 is positive or negative in this case). The second differential input of the third comparator 242 is connected to the third threshold voltage 240 (as a positive differential input signal) and the first threshold voltage 220 (as a negative differential input signal). In this manner, the third comparator 242 performs a comparison of the differential input signal 250 to a differential threshold signal provided by the third and first threshold voltages 240, 220, and outputs an indication of whether the differential input signal 250 is higher or lower than the differential threshold signal provided by the third and first threshold voltages 240, 220. The outputs of the comparators 222, 232, 242 are operably coupled to binary conversion logic 260, which outputs a 2-bit value based on the indications received from the comparators 222, 232, 242.
A problem with this known differential solution is that it results in suboptimal comparator design, due to the use of at least two differential pairs. Each differential pair contributes to the comparator offset, thereby resulting in a net increase in offset voltage. In addition, such design either exhibits limited linearity performance, which subsequently requires the use of degeneration, which in turn results in an increase in offset voltage, or the design exhibits sensitivity to differences in the common mode voltage of the input and the reference.
FIG. 3 illustrates a simplified example of an ADC circuit 300 proposed in a paper entitled “A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution” by Paton et al, published in the IEEE Journal of Solid-State Circuits, July 2004. Here, an input signal is first converted to a current. For the illustrated example, the input signal comprises analogue differential input voltage signals 305, which are converted to differential current signals by way of transconductor 310. The differential current signals output by the transconductor 310 are provided to a differential voltage ladder 320, which comprises a pair of resistor strings 340, 350 for converting received current signals into voltage signals 342, 344, 346, 352, 354, 356 that are provided to inputs of comparators 362, 364, 366. In addition to the differential currents resulting from the input signals 305, the transconductor 310 produces a common mode current, which also flows through the resistors. An additional common mode current component is provided to each of the resistor strings 340, 350 by transistors 330, 335. The combination of these common mode currents creates a DC voltage drop across each of the resistors in the voltage ladder 320. These DC voltage drops appear in the voltage signals 342, 344, 346, 352, 354, 356 provided to the inputs of the comparators 362, 364, 366, and represent the necessary thresholds for the comparators. Using the superposition principal, the signals received by the inputs of the comparators 362, 364, 366 comprise the combination of the differential input signals and the threshold voltages.
An advantage provided by the arrangement of FIG. 3 is that by combining the input signal and the thresholds before they are applied to the comparators, zero threshold comparators may be used. These zero threshold comparators are more robust and power efficient compared to comparators that process the input signal and thresholds separately, such as those used in the arrangements of FIGS. 1 and 2.
However, a problem with the arrangement of FIG. 3 is that the threshold voltages with which the input signal is combined are susceptible to changes in supply voltages, bias current changes, temperature changes, manufacturing process changes, device mismatches in the transconductance (or D/A converter for digital inputs), etc. As a result, the threshold voltages are susceptible to variations that cause changes to the flash transfer characteristics, i.e. the relation between the input and the output. Such a change in flash transfer characteristics effectively results in a gain change. In applications where the flash converter is used as part of a feedback loop, for example within a Sigma Delta converter, this variation changes the loop gain and can therefore cause degradation in performance or even lead to instability. Such a gain variation can also cause distortion, for example in pipeline or cyclic converters. This is due to the fact that the thresholds are no longer where they should ideally be, and this can result in a low gain state or even saturation in the residue amplifier.
Thus, a need exists for an improved integrated circuit comprising threshold generation circuitry, an analogue-to-digital converter circuit, and a method therefor that may alleviate one or more of the aforementioned problems of known threshold or ADC circuits.